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上一条:28. Zhenyu Deng*, Jiajia Jiang, Jilong Zhang, Yanchao Li, En Bo, Signal identification and filtering method based on synchronous integrated period sampling, Manufacturing Automation, vol.36, no.6,pp. 68-70, 2014.
下一条:26. Jun Xue, Fajie Duan, Jiajia Jiang*, Yanchao Li, Jianfu Yuan, Xianquan Wang, Parallel cyclic redundancy check Verilog program generating method based on Matlab, Journal of Computer Applications, vol. 36, no.9, pp.2503-2507, 2016.