天津大学教师个人主页系统吴志鹏 An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA Home

中文

Selected Papers

Date of Publication:2024-06-04Hits:

Journal:IEEE Embedded Systems Letters
All the Authors:Xiaodi Yin；Zhipeng Wu；Dejian Li；Chongfei Shen；Yu Liu
First Author:Xiaodi Yin
Correspondence Author:Yu Liu
Document Code:10.1109/LES.2023.3296507
Volume:16
Issue:2
Page Number:158-161
Translation or Not:no
CN No.:null
Date of Publication:2024-06-04

Pre One:Design and implementation of RISC-V system-on-chip for SPWM generation based on FPGA
Next One:HAOT: Heterogeneous Hardware-aware Tensor Computation Optimization Framework via Transformer

+

Wu Zhipeng

Click:

The Last Update Time:--

Address: No. 92, Weijin Road, Nankai District, Tianjin Zip Code: 300072