天津大学教师个人主页系统吴志鹏 Design and implementation of RISC-V system-on-chip for SPWM generation based on FPGA Home

中文

Selected Papers

Date of Publication:2024-12-25Hits:

Journal:IEICE Electronics Express
All the Authors:Qianxi Yin；Dejian Li；Zhipeng Wu；Sio Hang Pun；Yu Liu
First Author:Qianxi Yin
Correspondence Author:Yu Liu
Document Code:10.1109/LES.2023.3296507
Volume:21
Issue:24
Page Number:1-6
Translation or Not:no
CN No.:null
Date of Publication:2024-12-25

Pre One:GAS: A Flexible CNN Accelerator Architecture for Heterogeneous Dataflow Implementation
Next One:An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

+

Wu Zhipeng

Click:

The Last Update Time:--

Address: No. 92, Weijin Road, Nankai District, Tianjin Zip Code: 300072