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孟凡易
- 教师拼音名称：Meng Fanyi
- 出生日期：1987-11-30
- 性别：男
- 职称：教授
- 所属院系：微电子学院
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· B. Liu et al., "A 132-to-148GHz CMOS 4TX-4RX FMCW Radar Transceiver Array with Cavity-Backed Antenna-in-Package Achieving 28dBm EIRP," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, pp. 1-3, doi: 10.1109/ISSCC49661.2025.10904524.
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· Z. Ma, K. Ma, K. Wang and F. Meng, "A 28GHz Compact 3-Way Transformer-Based Parallel-Series Doherty Power Amplifier With 20.4%/14.2% PAE at 6-/12-dB Power Back-off and 25.5dBm PSAT in 55nm Bulk CMOS," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 320-322, doi: 10.1109/ISSCC42614.2022.9731564.
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· K. Li, K. Wang, F. Meng, K. S. Yeo and K. Ma, "Design and Analysis of a 13.7--41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure," in IEEE Journal of Solid-State Circuits, vol. 61, no. 8, pp. 3981-3995, Aug. 2026, doi: 10.1109/JSSC.2026.3667289.
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· J. Wu et al., "A Tripolar Spatiotemporal Stimulator With Return-Electrode-Based Charge-Pack Injection Technique for Charge Imbalance Correction," in IEEE Journal of Solid-State Circuits, vol. 61, no. 3, pp. 1068-1081, March 2026, doi: 10.1109/JSSC.2025.3623450.
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· Z. Yang, F. Meng, B. Liu, N. Zhu, Z. Zhao and K. Ma, "A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 60, no. 10, pp. 3843-3858, Oct. 2025, doi: 10.1109/JSSC.2025.3553760.
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· R. Wu et al., "A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation," in IEEE Journal of Solid-State Circuits, vol. 60, no. 5, pp. 1554-1569, May 2025, doi: 10.1109/JSSC.2025.3529681.
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· Z. Yang, K. Ma, F. Meng and B. Liu, "A 120-GHz Class-F Frequency Doubler With 7.8-dBm POUT in 55-nm Bulk CMOS," in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2173-2188, Aug. 2023, doi: 10.1109/JSSC.2023.3253287.
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· Z. Zhao et al., "Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications," in IEEE Journal of Solid-State Circuits, vol. 60, no. 9, pp. 3189-3201, Sept. 2025, doi: 10.1109/JSSC.2025.3545463.
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· Y. Zhang, N. Zhu, F. Meng, K. Wang, K. Ma and K. S. Yeo, "Design and Analysis of a Compact CMOS SOI Power Amplifier With 29.2-dBm PSAT and 44.4% PAE for FR3 5G-Advanced/6G Beamforming Systems," in IEEE Journal of Solid-State Circuits, vol. 61, no. 7, pp. 3393-3406, July 2026, doi: 10.1109/JSSC.2025.3639947.
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· Y. Zhang, N. Zhu, F. Meng, K. Wang, K. Ma and K. Seng Yeo, "A 6–10.1-GHz Compact CMOS SOI Power Amplifier Using a 6:1 Dual-Mode-Optimized Interleaved Transformer for Portable Radar and ISAC Front Ends," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2026.3719376.
