Qiang Liu
School
School of Microelectronics
Professional Title
Professor
Discipline
电子科学与技术
Contact Information
qiangliu@tju.edu.cn
Brief Introduction
Dr. Qiang Liu is a Professor in School of Microelectronics, Tianjin University. He received the Ph.D. degree from Department of Electrical and Electronic Engineering at Imperial College London, London, U.K., in 2008. From 2004 to 2005, he worked for STMicroelectronics Co. Ltd, Beijing, China. From 2009 to 2011, he was a Research Associate in Department of Computing at Imperial College London. In 2009 he received the Eryl Cadwaladr Davies Prize for producing the best doctoral thesis in Department of Electrical and Electronic Engineering at Imperial College London and the Runner-up in the 2009 CPHC/BCS Distinguished Dissertation Competition. In 2011 he joined in the School of Electronic Information Engineering, which is now School of Microelectronics, at Tianjin University.
His research interests include high speed and low power digital integrated circuit design and its applications in AI, telecommunication, signal processing and so on. He has published over 50 peer-reviewed papers and applied over 20 patents. He was the general chair of 2019 IEEE international conference on field-programmable technology, the TPC of 2020 IEEE international conference on field-programmable technology and of 2022 Asian Hardware Oriented Security and Trust Symposium.
Research Interests
- Reconfigurable computing, VLSI design automation and optimization, high speed and low power design, and IC security.
Academic Achievements
- Papers
- [1] Q. Liu, K. Masselos and G. A. Constantinides, "Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm," 2006 International Conference on Field Programmable Logic and Applications, Madrid, 2006, pp. 1-6, doi: 10.1109/FPL.2006.311242.
- [2] Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Automatic On-chip Memory Minimization for Data Reuse," 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), Napa, CA, 2007, pp. 251-260, doi: 10.1109/FCCM.2007.18.
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- [3] Qiang Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework," 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, 2008, pp. 179-184, doi: 10.1109/FPL.2008.4629928.
- [4] Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 305-315, March 2009, doi: 10.1109/TCAD.2009.2013541.
- [5] Q. Liu, T. Todman, J. G. de F. Coutinho, W. Luk and G. A. Constantinides, "Optimising designs by combining model-based and pattern-based transformations," 2009 International Conference on Field Programmable Logic and Applications, Prague, 2009, pp. 308-313, doi: 10.1109/FPL.2009.5272283.
- [6] Q. Liu, T. Todman, W. Luk and G. A. Constantinides, "Automatic optimisation of MapReduce designs by geometric programming," 2009 International Conference on Field-Programmable Technology, Sydney, NSW, 2009, pp. 215-222, doi: 10.1109/FPT.2009.5377629.
- [7] Q. Liu, T. Todman and W. Luk, "Combining optimizations in automated low power design," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, pp. 1791-1796, doi: 10.1109/DATE.2010.5457104.
- [8] T. Todman, Q. Liu, W. Luk and G. Constantinides, "A Scripting Engine for Combining Design Transformations," 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, Charlotte, NC, 2010, pp. 255-258, doi: 10.1109/FCCM.2010.46.
- [9] T. Todman, Q. Liu, W. Luk and G. Constantinides, "Customizable Composition and Parameterization of Hardware Design Transformations," 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Lille, 2010, pp. 595-602, doi: 10.1109/DSD.2010.78.
- [10] Q. Liu, T. Todman, K. H. Tsoi and W. Luk, "Convex models for accelerating applications on FPGA-based clusters," 2010 International Conference on Field-Programmable Technology, Beijing, 2010, pp. 495-498, doi: 10.1109/FPT.2010.5681466.
- [11] Q. Liu, G.A. Constantinides, K. Masselos and P.Y.K. Cheung, Compiling C-like languages to FPGA hardware: some novel approaches targeting data memory organisation, The Computer Journal, volume 54, issue 1, pp. 1-10, 2011.
- [12] Q. Liu, T. Mak, J. Luo, W. Luk and A. Yakovlev, "Power adaptive computing system design in energy harvesting environment," 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, 2011, pp. 33-40, doi: 10.1109/SAMOS.2011.6045442.
- [13] Q. Liu and W. Luk, "Objective-driven workload allocation in heterogeneous computing systems," 2011 International Conference on Field-Programmable Technology, New Delhi, 2011, pp. 1-4, doi: 10.1109/FPT.2011.6132695.
- [14] Q. Liu, T. Todman, W. Luk and G. A. Constantinides, "Optimizing Hardware Design by Composing Utility-Directed Transformations," in IEEE Transactions on Computers, vol. 61, no. 12, pp. 1800-1812, Dec. 2012, doi: 10.1109/TC.2011.205.
- [15] X. Niu, Q. Jin, W. Luk, Q. Liu and O. Pell, "Exploiting run-time reconfiguration in stencil computation," 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, 2012, pp. 173-180, doi: 10.1109/FPL.2012.6339257.
- [16] Q. Liu, J. Ma and Q. Zhang, "Neural network based pre-placement wirelength estimation," 2012 International Conference on Field-Programmable Technology, Seoul, 2012, pp. 16-22, doi: 10.1109/FPT.2012.6412104.
- [17] X. Niu, T. C. P. Chau, Q. Jin, W. Luk and Q. Liu, "Automating Elimination of Idle Functions by Run-Time Reconfiguration," 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, 2013, pp. 97-104, doi: 10.1109/FCCM.2013.58.
- [18] Q. Liu, Z. Xu and Y. Yuan, "A 66.1 Gbps single-pipeline AES on FPGA," 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, 2013, pp. 378-381, doi: 10.1109/FPT.2013.6718392.
- [19] H. Li and Q. Liu, "Hardware Trojan detection acceleration based on word-level statistical properties management," 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, 2014, pp. 153-160, doi: 10.1109/FPT.2014.7082769.
- [20] Q. Liu, Z. Xu, and Y. Yuan, High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion, IET Computers & Digital Techniques, Volume 9, Issue 3, pp. 175--184, May 2015.
- [21] Q. Liu, T. Mak, T. Zhang, X. Niu, W. Luk and A. Yakovlev, "Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1402-1414, Aug. 2015, doi: 10.1109/TVLSI.2014.2342213.
- [22] Qi Chen and Qiang Liu, "Pipelined NoC router architecture design with buffer configuration exploration on FPGA," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1-4, doi: 10.1109/FPL.2015.7293981.
- [23] Q. Liu and H. Li, "Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness," 2015 Euromicro Conference on Digital System Design, Funchal, 2015, pp. 599-605, doi: 10.1109/DSD.2015.19.
- [24] H. Li, Q. Liu, J. Zhang and Y. Lyu, "A Survey of Hardware Trojan Detection, Diagnosis and Prevention," 2015 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics), Xi'an, 2015, pp. 173-180, doi: 10.1109/CADGRAPHICS.2015.41.
- [25] Q. Liu, M. Gao and Q. Zhang, "Knowledge-Based Neural Network Model for FPGA Logical Architecture Development," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 664-677, Feb. 2016, doi: 10.1109/TVLSI.2015.2412958.
- [26] Q. Liu, W. Ji, Q. Chen and T. Mak, "IP Protection of Mesh NoCs Using Square Spiral Routing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1560-1573, April 2016, doi: 10.1109/TVLSI.2015.2462842.
- [27] Q. Liu, M. Gao, T. Zhang and Q.J. Zhang, Feedforward neural network models for FPGA routing channel width estimation, Chinese Journal of Electronics, vol.25, no.1, 2016.
- [28] Q. Liu and Q. Zhang, "Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2062-2074, June 2016, doi: 10.1109/TVLSI.2015.2497147.
- [29] T. Li and Q. Liu, "Cost Effective Partial Scan for Hardware Emulation," 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, 2016, pp. 131-134, doi: 10.1109/FCCM.2016.39.
- [30] R. Sang, Q. Liu and Q. Zhang, "FPGA-based acceleration of neural network training," 2016 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Beijing, 2016, pp. 1-2, doi: 10.1109/NEMO.2016.7561676.
- [31] Song Xu, Qiang Liu, Tao Li and Hongxiang Fan, "IC security evaluation against fault injection attack based on FPGA emulation," 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 285-288, doi: 10.1109/FPT.2016.7929554.
- [32] Jiajun Li and Qiang Liu. 2017. Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL. In Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017). Association for Computing Machinery, New York, NY, USA, Article 17, 1–6.
- [33] Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk and Qiang Liu, “Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms,” ARC 2017: Applied Reconfigurable Computing pp 255-267,2017
- [34] Q. Liu and H. Qian, "FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters," 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 29-29, doi: 10.1109/FCCM.2017.16.
- [35] F. Chen and Q. Liu, "Single-triggered hardware Trojan identification based on gate-level circuit structural characteristics," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050673.
- [36] H. Fan, X. Niu, Q. Liu and W. Luk, "F-C3D: FPGA-based 3-dimensional convolutional neural network," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1-4, doi: 10.23919/FPL.2017.8056779.
- [37] Liu, Q. and Qian, H. (2017), Fast and accurate circuit delay model for FPGA architectural exploration. IET Comput. Digit. Tech., 11: 117-123. https://doi.org/10.1049/iet-cdt.2016.0053
- [38] T. Li and Q. Liu, "A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 5, pp. 1109-1113, May 2018, doi: 10.1109/TCAD.2017.2729348.
- [39] Q. Liu, J. Liu, R. Sang, J. Li, T. Zhang and Q. Zhang, "Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1575-1579, Aug. 2018, doi: 10.1109/TVLSI.2018.2820016.
- [40] B. Ning and Q. Liu, "Modeling and Efficiency Analysis of Clock Glitch Fault Injection Attack," 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, 2018, pp. 13-18, doi: 10.1109/AsianHOST.2018.8607175.
- [41] J. Liu and Q. Liu, "Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix Updating," 2018 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, 2018, pp. 301-306, doi: 10.1109/FPL.2018.00058.
- [42] J. Liu and Q. Liu, "Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network Training," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 362-365, doi: 10.1109/FPT.2018.00074.
- [43] Li, H., Liu, Q. and Chen, F. (2018), Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. IET Comput. Digit. Tech., 12: 258-267. https://doi.org/10.1049/iet-cdt.2018.5101
- [44] Q. Liu, P. Zhao and F. Chen, "A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits," in IEEE Access, vol. 7, pp. 44632-44644, 2019, doi: 10.1109/ACCESS.2019.2908088.
- [45] Q. Liu, B. Ning and P. Deng, "Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks," in IEEE Access, vol. 7, pp. 141920-141928, 2019, doi: 10.1109/ACCESS.2019.2944024.
- [46] S. Yan, Q. Liu, J. Li and L. Han, "Heterogeneous Acceleration of Hybrid PSO-QN Algorithm for Neural Network Training," in IEEE Access, vol. 7, pp. 161499-161509, 2019, doi: 10.1109/ACCESS.2019.2951710.
- [47] P. Zhao and Q. Liu, "Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features," 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi'an, China, 2019, pp. 1-4, doi: 10.1109/AsianHOST47458.2019.9006695.
- [48] S. Qin, Q. Liu, B. Yu and S. Liu, "π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization," 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, USA, 2019, pp. 100-108, doi: 10.1109/FCCM.2019.00024.
- [49] Y. Jiang, Q. Liu, H. Cao and Y. Song, "Peak Detection Based on FPGA Using Quasi-Newton Optimization Method for Femtosecond Laser Ranging," in IEEE Access, vol. 8, pp. 47776-47786, 2020, doi: 10.1109/ACCESS.2020.2979268.
- [50] Q. Liu, S. Qin, B. Yu, J. Tang and S. Liu, "π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations," in IEEE Transactions on Computers, vol. 69, no. 7, pp. 1083-1095, 1 July 2020, doi: 10.1109/TC.2020.2984611.
- [51] Yiming Gan; Yu Bo; Boyuan Tian; Leimeng Xu; Wei Hu; Shaoshan Liu; Qiang Liu; Yanjun Zhang; Jie Tang; Yuhao Zhu, "Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines Industry Track Paper," 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, pp. 827-840, doi: 10.1109/HPCA51647.2021.00074.
- [52] Shun Yan; Zhengyan Liu; Yun Wang; Chenglong Zeng; Qiang Liu; Bowen Cheng; Ray C.C. Cheung, "An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics," 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, pp. 17-23, doi: 10.1109/FPL53798.2021.00011
- [53] M. Zhang and Q. Liu, "Experimental Verification of EMPA Fault Mechanism," 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021, pp. 1-6, doi: 10.1109/NANOARCH53687.2021.9642244.
- [54] Qiang Liu, Honghui Tang, and Peiran Zhang. Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs. ACM Trans. Des. Autom. Electron. Syst. 27, 1, Article 8, October 2021, 25 pages. https://doi.org/10.1145/3480962.
- [55] M. Zhang and Q. Liu, "A Digital and Lightweight Delay-Based Detector against Fault Injection Attacks," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401185.
- [56] C. Yao, Q. Liu, L. Wang, Q. Zhang, H. Tang and M. Zhang, "Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on FPGA," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401652.
- [57] H. Li, A. Abdelhadi, R. Shi, J. Zhang and Q. Liu, "Adversarial Hardware with Functional and Topological Camouflage," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.68, No. 5，pp. 1685-1689, May 2021. doi: 10.1109/TCSII.2021.3065292.
- [58] H. Tang and Q. Liu, "MPFA: an efficient multiple faults-based persistent fault analysis method for low-cost FIA," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2021.3117512.
- [59] Weizhuang Liu, Bo Yu, Yiming Gan, Qiang Liu, Jie Tang, Shaoshan Liu, and Yuhao Zhu. 2021. Archytas: A Framework for Synthesizing and Dynamically Optimizing Accelerators for Robotic Localization. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '21). Association for Computing Machinery, New York, NY, USA, 479–493. https://doi.org/10.1145/3466752.3480077
- [60] Zhang, Z., Liu, Q., Guo, D. (2021). Knowledge-Based Multiple Lightweight Attribute Networks for Zero-Shot Learning. In: Mantoro, T., Lee, M., Ayu, M.A., Wong, K.W., Hidayanto, A.N. (eds) Neural Information Processing. ICONIP 2021. Communications in Computer and Information Science, vol 1516. Springer, Cham.
- [61] J. Jiao, H. Li, Y. Feng, C. Qian and Q. Liu, "In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU," 2022 IEEE 35th International System-on-Chip Conference (SOCC), 2022, pp. 1-6, doi: 10.1109/SOCC56010.2022.9908097.
- [62] Y. Wang, Q. Liu and S. Yan, "DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators," 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2022, pp. 1-1, doi: 10.1109/FCCM53951.2022.9786195.
- [63] Q. Liu, Z. Wan, B. Yu, W. Liu, S. Liu and A. Raychowdhury, "An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems," 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, pp. 01-02, doi: 10.1109/CICC53496.2022.9772870.
- [64] M. Zhang, H. Li and Q. Liu, "Deep Exploration on Fault Model of Electromagnetic Pulse Attack," in IEEE Transactions on Nanotechnology, vol. 21, pp. 598-605, 2022, doi: 10.1109/TNANO.2022.3214341.