刘强，天津大学微电子学院教授，博导。2008年博士毕业于英国伦敦帝国理工学院电子系。2009-2011年，英国伦敦帝国理工学院计算机系高级助理研究员。2011任职于天津大学。目前担任天津市边缘计算重点实验室学术委员会主任、中国密码学会密码芯片专委会委员、图像智能边缘计算专业委员会委员、《电子与信息学报》第九届编委会委员。曾担任2023年亚洲硬件安全国际会议大会主席、2019 IEEE现场可编程技术国际会议(FPT)大会主席、IEEE Transactions on Circuits and Systems-I新兴硬件安全和可信技术专刊客座编委。

研究领域包括（1）高速低功耗数字集成电路设计方法，及其在通信、信号处理、人工智能等领域的应用。（2）集成电路硬件安全，包括集成电路IP保护、安全评估、故障注入攻击攻防关键技术研究等。以第一作者/通讯作者发表学术论文100余篇。作为负责人承担国家自然科学基金项目5项、天津市应用基础及前沿技术研究计划一般项目1项、教育部留学归国科研启动基金1项、Alibaba Innovative Research项目等技术开发项目多项。

• 定制化计算，高速低功耗电路设计，人工智能加速器设计，集成电路硬件安全。

• 宝钢教师奖
• 国家级一流课程负责人
• 2017 Premium Award for Best Paper in IET Computers & Digital Techniques

• M. Wang, Y. Han, Y. Mao, P. Shao, Z. Liu and Q. Liu, "SDTA: An Efficient Sparse DNN Training Accelerator with Data Hierarchical Pre-fetching and Dynamic Scheduling," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5,
• Zhen Gao; Yanmao Qi; Jinchang Shi; Qiang Liu; Guangjun Ge; Yu Wang, "Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 1, pp. 66-74, Jan. 2025, doi: 10.1109/TVLSI.2024.3443834.
• Z. Gao, L. Yuan, J. Wang, Q. Liu, J. Conde, P. Reviriego, "Robustness Against Faults in Configuration Memories of FPGA-Based LLMs," in IEEE Transactions on Circuits and Systems for Artificial Intelligence, vol. 2, no. 2, pp. 162-173, June 2025.
• Z. Gao， Z. Yin, J. Wang, R. Su, J. Deng, Q. Liu, P. Reviriego, S. Liu and F. Lombardi, "On the Dependability of Bidirectional Encoder Representations from Transformers (BERT) to Soft Errors," in IEEE Transactions on Nanotechnology, vol. 24, pp. 73-87, 2025
• Zhongyu Guan, Qiang Liu, and Guangdong Lin. 2025. ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier. Proceedings of the 30th Asia and South Pacific Design Automation Conference. Association for Computing Machinery, New York, NY, USA, 218–223. https://doi.org/10.1145/3658617.3697710
• Luo, W., Guo, Z., Liu, Q. (2025). An Efficient DNN Training Method with Progressive Pruning. In: Huang, DS., Chen, W., Pan, Y., Chen, H. (eds) Advanced Intelligent Computing Technology and Applications. ICIC 2025. Lecture Notes in Computer Science(), vol 15863. Springer, Singapore. https://doi.org/10.1007/978-981-95-0009-3_42
• Mingyu Shu and Qiang Liu. 2025. LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing. ACM Trans. Reconfigurable Technol. Syst. October 2025. https://doi.org/10.1145/3770757
• Qiang Liu, Yihao Hua, Yuhui Hao, Bo Yu, Shaoshan Liu, and Yiming Gan. 2025. Unified and Efficient Factor Graph Accelerator Design for Robotic Optimization. ACM Trans. Archit. Code Optim. Just Accepted (October 2025). https://doi.org/10.1145/3771846
• Yuan, M., Liu, Q. & Gan, L. An FPGA-based efficient accelerator for fault interaction of rupture dynamics. J Supercomput 81, 1323 (2025). https://doi.org/10.1007/s11227-025-07801-x
• Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, and Yiming Gan. 2025. Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation. In Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA '25). Association for Computing Machinery, New York, NY, USA, 327–343. https://doi.org/10.1145/3695053.3731099
• X. Liu and Q. Liu, "HNMC: Hybrid Near-Memory Computing Circuit for Neural Network Acceleration," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 11, pp. 4763-4767, Nov. 2024, doi: 10.1109/TCSII.2024.3403830.
• M. Yuan, Q. Liu, L. Gan and G. Yang, "ESFLOW: Mapping Large-Scale Earthquake Simulation to Spatial Computing Systems," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558278.
• Y. Mao, M. Shu and Q. Liu, "PBN: Progressive Batch Normalization for DNN Training on Edge Device," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558569.
• M. Shu, Y. Mao and Q. Liu, "A Data-Distribution Aware Approximate Multiplier Design Based on FPGA," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10557930.
• J. Wei and Q. Liu, "A Fault Attack Resistant Method for RISC-V Based on Interrupt Handlers and Instruction Extensions," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558427.
• Y. Mao, Q. Liu and R. C. C. Cheung, "MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training," 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Hong Kong, Hong Kong, 2024, pp. 34-35, doi: 10.1109/ASAP61560.2024.00019.
• Y. Wang and Q. Liu, "AQA: An Adaptive Post-Training Quantization Method for Activations of CNNs," in IEEE Transactions on Computers, vol. 73, no. 8, pp. 2025-2035, Aug. 2024, doi: 10.1109/TC.2024.3398503.
• Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, and Shaoshan Liu. 2024. ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2 (ASPLOS '24), Vol. 2. Association for Computing Machinery, New York, NY, USA, 813–829. https://doi.org/10.1145/3620665.3640379
• Z. Guo; Z. Gao; Q. Liu; L. Liu; M. Dong; N. Zhang; M. Atiquzzaman, "Modular-based Compression Scheme for Address Data in the Blockchain System for IoV Applications," in IEEE Transactions on Vehicular Technology, vol. 73, no. 10, pp. 15567-15583, Oct. 2024 doi: 10.1109/TVT.2024.3411568
• Quan Deng; Qiang Liu; Ming Yuan; Xiaohui Duan; Lin Gan; Jinzhe Yang, "Acceleration of Multi-body Molecular Dynamics with Customized Parallel Dataflow," in IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 12, pp. 2297-2314, Dec. 2024, doi: 10.1109/TPDS.2024.3420441.
• Guo, Zhaohui, Gao, Zhen, Liu, Qiang, Liu, Lei, Dong, Mianxiong, Zhang, Ning, Atiquzzaman, Mohammed, "Verkle-Accumulator-Based Stateless Transaction Validation (VA-STV) Scheme for the Blockchain-Based IoT Network," in IEEE Internet of Things Journal, vol. 11, no. 1, pp. 543-558, 1 Jan.1, 2024, doi: 10.1109/JIOT.2023.3287210.
• L. Guo and Q. Liu, "A DRAM Chip Protection Method Against EMFI Based on PHOTON Hash," 2024 IEEE International Test Conference in Asia (ITC-Asia), Changsha, China, 2024, pp. 1-6, doi: 10.1109/ITC-Asia62534.2024.10661316
• Z. Gao， J. Feng, S. Gao, Q. Liu*, G. Gen, Y. Wang and P. Reviriego, “Modeling the Effect of SEUs on the Configuration Memory of SRAM-FPGA-Based CNN Accelerators," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 4, pp. 799-810, Dec. 2024.
• Y. Han, H. Li and Q. Liu, "Efficient Table-Lookup Inference of Binarized Convolutions with Kernel-Level Binding on FPGA," 2024 International Conference on Field Programmable Technology (ICFPT), Sydney, Australia, 2024, pp. 1-2, doi: 10.1109/ICFPT64416.2024.11113449.
• Z. Gao, J. Shi, Q. Liu, A. Ullah and P. Reviriego, "Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 1, pp. 142-146, Jan. 2023, doi: 10.1109/TVLSI.2022.3224137.
• Zhen Gao, Shihui Gao, Yi Yao, Qiang Liu, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego, "Systematic Reliability Evaluation of FPGA Implemented CNN Accelerators," in IEEE Transactions on Device and Materials Reliability, vol. 23, no. 1, pp. 116-126, March 2023, doi: 10.1109/TDMR.2023.3235767.
• Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu, and Yuhao Zhu. 2022. Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper). In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD '22). Association for Computing Machinery, New York, NY, USA, Article 103, 1–7. https://doi.org/10.1145/3508352.3561112
• Q. Liu, L. Guo and H. Tang, "Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6, doi: 10.23919/DATE56975.2023.10137146.
• K. Li, W. Yin and Q. Liu, "A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions," 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181681.
• Y. Wang and Q. Liu, "An Adaptive Quantization Method for CNN Activations," 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181695.
• Y. Hao, Y. Gan, B. Yu, Q. Liu, S. -S. Liu and Y. Zhu, "BLITZCRANK: Factor Graph Accelerator for Motion Planning," 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2023, pp. 1-6, doi: 10.1109/DAC56929.2023.10247780.
• Y. Han and Q. Liu, "HPTA: A High Performance Transformer Accelerator Based on FPGA," 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 2023, pp. 27-33, doi: 10.1109/FPL60245.2023.00012.
• Z. Gao, Y. Cheng, Q. Liu, A. Ullah and P. Reviriego, "Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3770-3780, Sept. 2023, doi: 10.1109/TCSI.2023.3279444.
• Qiang Liu, Yuhui Hao, Weizhuang Liu, Bo Yu*, Yiming Gan, Jie Tang*, Shao-Shan Liu and Yuhao Zhu*, "An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization," in IEEE Transactions on Computers, vol. 72, no. 7, pp. 1943-1957, 1 July 2023, doi: 10.1109/TC.2022.3230899.
• Z. Gao, J. Xiao, Q. Liu, A. Ullah and P. Reviriego, "A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 2003-2015, May 2023, doi: 10.1109/TCSI.2023.3239040.
• Deng, Quan, Liu, Qiang, “Field-programmable gate array acceleration of the Tersoff potential in LAMMPS,” in ENGINEERING REPORTS,
• Liu, Zhengyan and Liu, Qiang and Yan, Shun and Cheung, Ray C.C. , “An Efficient FPGA-Based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning”, ACM Trans. Reconfigurable Technol. Syst., Sept. 2023
• Y. Mao and Q. Liu, "An FPGA-based Mix-grained Sparse Training Accelerator," 2023 International Conference on Field Programmable Technology (ICFPT), Yokohama, Japan, 2023, pp. 276-277, doi: 10.1109/ICFPT59805.2023.00043.
• Zhang M, Li H, Wang P, Liu Q. Parity Check Based Fault Detection against Timing Fault Injection Attacks. Electronics. 2022; 11(24):4082.
• M. Shu and Q. Liu, "LCAM: Low-Cost Approximate Multiplier Design on FPGA," 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, 2022, pp. 1-1, doi: 10.1109/ICFPT56656.2022.9974375.
• H. Tang and Q. Liu, "MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 9, pp. 2821-2834, Sept. 2022, doi: 10.1109/TCAD.2021.3117512.
• Zhaohui Guo; Zhen Gao; Qiang Liu; Chinmay Chakraborty; Qiaozhi Hua; Keping Yu, "RNS-Based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT," in IEEE Transactions on Industrial Informatics, vol. 18, no. 12, pp. 9239-9249, Dec. 2022, doi: 10.1109/TII.2022.3182766.
• Q. Liu, K. Masselos and G. A. Constantinides, "Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm," 2006 International Conference on Field Programmable Logic and Applications, Madrid, 2006, pp. 1-6, doi: 10.1109/FPL.2006.311242.
• Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Automatic On-chip Memory Minimization for Data Reuse," 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), Napa, CA, 2007, pp. 251-260, doi: 10.1109/FCCM.2007.18.
• Qiang Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework," 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, 2008, pp. 179-184, doi: 10.1109/FPL.2008.4629928.
• Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 305-315, March 2009, doi: 10.1109/TCAD.2009.2013541.
• Q. Liu, T. Todman, J. G. de F. Coutinho, W. Luk and G. A. Constantinides, "Optimising designs by combining model-based and pattern-based transformations," 2009 International Conference on Field Programmable Logic and Applications, Prague, 2009, pp. 308-313, doi: 10.1109/FPL.2009.5272283.
• Q. Liu, T. Todman, W. Luk and G. A. Constantinides, "Automatic optimisation of MapReduce designs by geometric programming," 2009 International Conference on Field-Programmable Technology, Sydney, NSW, 2009, pp. 215-222, doi: 10.1109/FPT.2009.5377629.
• Q. Liu, T. Todman and W. Luk, "Combining optimizations in automated low power design," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, pp. 1791-1796, doi: 10.1109/DATE.2010.5457104.
• T. Todman, Q. Liu, W. Luk and G. Constantinides, "A Scripting Engine for Combining Design Transformations," 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, Charlotte, NC, 2010, pp. 255-258, doi: 10.1109/FCCM.2010.46.
• T. Todman, Q. Liu, W. Luk and G. Constantinides, "Customizable Composition and Parameterization of Hardware Design Transformations," 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Lille, 2010, pp. 595-602, doi: 10.1109/DSD.2010.78.
• Q. Liu, T. Todman, K. H. Tsoi and W. Luk, "Convex models for accelerating applications on FPGA-based clusters," 2010 International Conference on Field-Programmable Technology, Beijing, 2010, pp. 495-498, doi: 10.1109/FPT.2010.5681466.
• Q. Liu, G.A. Constantinides, K. Masselos and P.Y.K. Cheung, Compiling C-like languages to FPGA hardware: some novel approaches targeting data memory organisation, The Computer Journal, volume 54, issue 1, pp. 1-10, 2011.
• Q. Liu, T. Mak, J. Luo, W. Luk and A. Yakovlev, "Power adaptive computing system design in energy harvesting environment," 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, 2011, pp. 33-40, doi: 10.1109/SAMOS.2011.6045442.
• Q. Liu and W. Luk, "Objective-driven workload allocation in heterogeneous computing systems," 2011 International Conference on Field-Programmable Technology, New Delhi, 2011, pp. 1-4, doi: 10.1109/FPT.2011.6132695.
• Q. Liu, T. Todman, W. Luk and G. A. Constantinides, "Optimizing Hardware Design by Composing Utility-Directed Transformations," in IEEE Transactions on Computers, vol. 61, no. 12, pp. 1800-1812, Dec. 2012, doi: 10.1109/TC.2011.205.
• X. Niu, Q. Jin, W. Luk, Q. Liu and O. Pell, "Exploiting run-time reconfiguration in stencil computation," 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, 2012, pp. 173-180, doi: 10.1109/FPL.2012.6339257.
• Q. Liu, J. Ma and Q. Zhang, "Neural network based pre-placement wirelength estimation," 2012 International Conference on Field-Programmable Technology, Seoul, 2012, pp. 16-22, doi: 10.1109/FPT.2012.6412104.
• X. Niu, T. C. P. Chau, Q. Jin, W. Luk and Q. Liu, "Automating Elimination of Idle Functions by Run-Time Reconfiguration," 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, 2013, pp. 97-104, doi: 10.1109/FCCM.2013.58.
• Q. Liu, Z. Xu and Y. Yuan, "A 66.1 Gbps single-pipeline AES on FPGA," 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, 2013, pp. 378-381, doi: 10.1109/FPT.2013.6718392.
• H. Li and Q. Liu, "Hardware Trojan detection acceleration based on word-level statistical properties management," 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, 2014, pp. 153-160, doi: 10.1109/FPT.2014.7082769.
• Q. Liu, Z. Xu, and Y. Yuan, High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion, IET Computers & Digital Techniques, Volume 9, Issue 3, pp. 175--184, May 2015.
• Q. Liu, T. Mak, T. Zhang, X. Niu, W. Luk and A. Yakovlev, "Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1402-1414, Aug. 2015, doi: 10.1109/TVLSI.2014.2342213.
• Qi Chen and Qiang Liu, "Pipelined NoC router architecture design with buffer configuration exploration on FPGA," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1-4, doi: 10.1109/FPL.2015.7293981.
• Q. Liu and H. Li, "Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness," 2015 Euromicro Conference on Digital System Design, Funchal, 2015, pp. 599-605, doi: 10.1109/DSD.2015.19.
• H. Li, Q. Liu, J. Zhang and Y. Lyu, "A Survey of Hardware Trojan Detection, Diagnosis and Prevention," 2015 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics), Xi'an, 2015, pp. 173-180, doi: 10.1109/CADGRAPHICS.2015.41.
• Q. Liu, M. Gao and Q. Zhang, "Knowledge-Based Neural Network Model for FPGA Logical Architecture Development," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 664-677, Feb. 2016, doi: 10.1109/TVLSI.2015.2412958.
• Q. Liu, W. Ji, Q. Chen and T. Mak, "IP Protection of Mesh NoCs Using Square Spiral Routing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1560-1573, April 2016, doi: 10.1109/TVLSI.2015.2462842.
• Q. Liu, M. Gao, T. Zhang and Q.J. Zhang, Feedforward neural network models for FPGA routing channel width estimation, Chinese Journal of Electronics, vol.25, no.1, 2016.
• Q. Liu and Q. Zhang, "Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2062-2074, June 2016, doi: 10.1109/TVLSI.2015.2497147.
• T. Li and Q. Liu, "Cost Effective Partial Scan for Hardware Emulation," 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, 2016, pp. 131-134, doi: 10.1109/FCCM.2016.39.
• R. Sang, Q. Liu and Q. Zhang, "FPGA-based acceleration of neural network training," 2016 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Beijing, 2016, pp. 1-2, doi: 10.1109/NEMO.2016.7561676.
• Song Xu, Qiang Liu, Tao Li and Hongxiang Fan, "IC security evaluation against fault injection attack based on FPGA emulation," 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 285-288, doi: 10.1109/FPT.2016.7929554.
• Jiajun Li and Qiang Liu. 2017. Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL. In Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017). Association for Computing Machinery, New York, NY, USA, Article 17, 1–6.
• Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk and Qiang Liu, “Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms,” ARC 2017: Applied Reconfigurable Computing pp 255-267,2017
• Q. Liu and H. Qian, "FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters," 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 29-29, doi: 10.1109/FCCM.2017.16.
• F. Chen and Q. Liu, "Single-triggered hardware Trojan identification based on gate-level circuit structural characteristics," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050673.
• H. Fan, X. Niu, Q. Liu and W. Luk, "F-C3D: FPGA-based 3-dimensional convolutional neural network," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1-4, doi: 10.23919/FPL.2017.8056779.
• Liu, Q. and Qian, H. (2017), Fast and accurate circuit delay model for FPGA architectural exploration. IET Comput. Digit. Tech., 11: 117-123. https://doi.org/10.1049/iet-cdt.2016.0053
• T. Li and Q. Liu, "A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 5, pp. 1109-1113, May 2018, doi: 10.1109/TCAD.2017.2729348.
• Q. Liu, J. Liu, R. Sang, J. Li, T. Zhang and Q. Zhang, "Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1575-1579, Aug. 2018, doi: 10.1109/TVLSI.2018.2820016.
• B. Ning and Q. Liu, "Modeling and Efficiency Analysis of Clock Glitch Fault Injection Attack," 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, 2018, pp. 13-18, doi: 10.1109/AsianHOST.2018.8607175.
• J. Liu and Q. Liu, "Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix Updating," 2018 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, 2018, pp. 301-306, doi: 10.1109/FPL.2018.00058.
• J. Liu and Q. Liu, "Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network Training," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 362-365, doi: 10.1109/FPT.2018.00074.
• Li, H., Liu, Q. and Chen, F. (2018), Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. IET Comput. Digit. Tech., 12: 258-267. https://doi.org/10.1049/iet-cdt.2018.5101
• Q. Liu, P. Zhao and F. Chen, "A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits," in IEEE Access, vol. 7, pp. 44632-44644, 2019, doi: 10.1109/ACCESS.2019.2908088.
• Q. Liu, B. Ning and P. Deng, "Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks," in IEEE Access, vol. 7, pp. 141920-141928, 2019, doi: 10.1109/ACCESS.2019.2944024.
• S. Yan, Q. Liu, J. Li and L. Han, "Heterogeneous Acceleration of Hybrid PSO-QN Algorithm for Neural Network Training," in IEEE Access, vol. 7, pp. 161499-161509, 2019, doi: 10.1109/ACCESS.2019.2951710.
• P. Zhao and Q. Liu, "Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features," 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi'an, China, 2019, pp. 1-4, doi: 10.1109/AsianHOST47458.2019.9006695.
• S. Qin, Q. Liu, B. Yu and S. Liu, "π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization," 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, USA, 2019, pp. 100-108, doi: 10.1109/FCCM.2019.00024.
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