Qiang Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework," 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, 2008, pp. 179-184, doi: 10.1109/FPL.2008.4629928.

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上一条:Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Automatic On-chip Memory Minimization for Data Reuse," 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), Napa, CA, 2007, pp. 251-260, doi: 10.1109/FCCM.2007.18. 下一条:Q. Liu, G. A. Constantinides, K. Masselos and P. Y. K. Cheung, "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 305-315, March 2009, doi: 10.1109/TCAD.2009.2013541.