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- 教师名称:刘强
- 教师拼音名称:Qiang Liu
- 性别:男
- 学科:电子科学与技术
- 职称:教授
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M. Wang, Y. Han, Y. Mao, P. Shao, Z. Liu and Q. Liu, "SDTA: An Efficient Sparse DNN Training Accelerator with Data Hierarchical Pre-fetching and Dynamic Scheduling," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5,
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Zhen Gao; Yanmao Qi; Jinchang Shi; Qiang Liu; Guangjun Ge; Yu Wang, "Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 1, pp. 66-74, Jan. 2025, doi: 10.1109/TVLSI.2024.3443834.
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Z. Gao, L. Yuan, J. Wang, Q. Liu, J. Conde, P. Reviriego, "Robustness Against Faults in Configuration Memories of FPGA-Based LLMs," in IEEE Transactions on Circuits and Systems for Artificial Intelligence, vol. 2, no. 2, pp. 162-173, June 2025.
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Z. Gao, Z. Yin, J. Wang, R. Su, J. Deng, Q. Liu, P. Reviriego, S. Liu and F. Lombardi, "On the Dependability of Bidirectional Encoder Representations from Transformers (BERT) to Soft Errors," in IEEE Transactions on Nanotechnology, vol. 24, pp. 73-87, 2025
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Zhongyu Guan, Qiang Liu, and Guangdong Lin. 2025. ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier. Proceedings of the 30th Asia and South Pacific Design Automation Conference. Association for Computing Machinery, New York, NY, USA, 218–223. https://doi.org/10.1145/3658617.3697710
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Luo, W., Guo, Z., Liu, Q. (2025). An Efficient DNN Training Method with Progressive Pruning. In: Huang, DS., Chen, W., Pan, Y., Chen, H. (eds) Advanced Intelligent Computing Technology and Applications. ICIC 2025. Lecture Notes in Computer Science(), vol 15863. Springer, Singapore. https://doi.org/10.1007/978-981-95-0009-3_42
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Mingyu Shu and Qiang Liu. 2025. LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing. ACM Trans. Reconfigurable Technol. Syst. October 2025. https://doi.org/10.1145/3770757
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Qiang Liu, Yihao Hua, Yuhui Hao, Bo Yu, Shaoshan Liu, and Yiming Gan. 2025. Unified and Efficient Factor Graph Accelerator Design for Robotic Optimization. ACM Trans. Archit. Code Optim. Just Accepted (October 2025). https://doi.org/10.1145/3771846
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Yuan, M., Liu, Q. & Gan, L. An FPGA-based efficient accelerator for fault interaction of rupture dynamics. J Supercomput 81, 1323 (2025). https://doi.org/10.1007/s11227-025-07801-x
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Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, and Yiming Gan. 2025. Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation. In Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA '25). Association for Computing Machinery, New York, NY, USA, 327–343. https://doi.org/10.1145/3695053.3731099
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X. Liu and Q. Liu, "HNMC: Hybrid Near-Memory Computing Circuit for Neural Network Acceleration," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 11, pp. 4763-4767, Nov. 2024, doi: 10.1109/TCSII.2024.3403830.
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M. Yuan, Q. Liu, L. Gan and G. Yang, "ESFLOW: Mapping Large-Scale Earthquake Simulation to Spatial Computing Systems," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558278.
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Y. Mao, M. Shu and Q. Liu, "PBN: Progressive Batch Normalization for DNN Training on Edge Device," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558569.
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M. Shu, Y. Mao and Q. Liu, "A Data-Distribution Aware Approximate Multiplier Design Based on FPGA," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10557930.
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J. Wei and Q. Liu, "A Fault Attack Resistant Method for RISC-V Based on Interrupt Handlers and Instruction Extensions," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558427.