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- 教师名称：刘强
- 教师拼音名称：Qiang Liu
- 性别：男
- 学科：电子科学与技术
- 职称：教授
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Q. Liu, J. Ma and Q. Zhang, "Neural network based pre-placement wirelength estimation," 2012 International Conference on Field-Programmable Technology, Seoul, 2012, pp. 16-22, doi: 10.1109/FPT.2012.6412104.
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X. Niu, T. C. P. Chau, Q. Jin, W. Luk and Q. Liu, "Automating Elimination of Idle Functions by Run-Time Reconfiguration," 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, 2013, pp. 97-104, doi: 10.1109/FCCM.2013.58.
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Q. Liu, Z. Xu and Y. Yuan, "A 66.1 Gbps single-pipeline AES on FPGA," 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, 2013, pp. 378-381, doi: 10.1109/FPT.2013.6718392.
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H. Li and Q. Liu, "Hardware Trojan detection acceleration based on word-level statistical properties management," 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, 2014, pp. 153-160, doi: 10.1109/FPT.2014.7082769.
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Q. Liu, Z. Xu, and Y. Yuan, High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion, IET Computers & Digital Techniques, Volume 9, Issue 3, pp. 175--184, May 2015.
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Q. Liu, T. Mak, T. Zhang, X. Niu, W. Luk and A. Yakovlev, "Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1402-1414, Aug. 2015, doi: 10.1109/TVLSI.2014.2342213.
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Qi Chen and Qiang Liu, "Pipelined NoC router architecture design with buffer configuration exploration on FPGA," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1-4, doi: 10.1109/FPL.2015.7293981.
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Q. Liu and H. Li, "Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness," 2015 Euromicro Conference on Digital System Design, Funchal, 2015, pp. 599-605, doi: 10.1109/DSD.2015.19.
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H. Li, Q. Liu, J. Zhang and Y. Lyu, "A Survey of Hardware Trojan Detection, Diagnosis and Prevention," 2015 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics), Xi'an, 2015, pp. 173-180, doi: 10.1109/CADGRAPHICS.2015.41.
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Q. Liu, M. Gao and Q. Zhang, "Knowledge-Based Neural Network Model for FPGA Logical Architecture Development," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 664-677, Feb. 2016, doi: 10.1109/TVLSI.2015.2412958.
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Q. Liu, W. Ji, Q. Chen and T. Mak, "IP Protection of Mesh NoCs Using Square Spiral Routing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1560-1573, April 2016, doi: 10.1109/TVLSI.2015.2462842.
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Q. Liu, M. Gao, T. Zhang and Q.J. Zhang, Feedforward neural network models for FPGA routing channel width estimation, Chinese Journal of Electronics, vol.25, no.1, 2016.
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Q. Liu and Q. Zhang, "Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2062-2074, June 2016, doi: 10.1109/TVLSI.2015.2497147.
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T. Li and Q. Liu, "Cost Effective Partial Scan for Hardware Emulation," 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, 2016, pp. 131-134, doi: 10.1109/FCCM.2016.39.
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R. Sang, Q. Liu and Q. Zhang, "FPGA-based acceleration of neural network training," 2016 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Beijing, 2016, pp. 1-2, doi: 10.1109/NEMO.2016.7561676.
