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- 教师名称：刘强
- 教师拼音名称：Qiang Liu
- 性别：男
- 学科：电子科学与技术
- 职称：教授
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Song Xu, Qiang Liu, Tao Li and Hongxiang Fan, "IC security evaluation against fault injection attack based on FPGA emulation," 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 285-288, doi: 10.1109/FPT.2016.7929554.
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Jiajun Li and Qiang Liu. 2017. Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL. In Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017). Association for Computing Machinery, New York, NY, USA, Article 17, 1–6.
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Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk and Qiang Liu, “Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms,” ARC 2017: Applied Reconfigurable Computing pp 255-267,2017
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Q. Liu and H. Qian, "FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters," 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 29-29, doi: 10.1109/FCCM.2017.16.
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F. Chen and Q. Liu, "Single-triggered hardware Trojan identification based on gate-level circuit structural characteristics," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050673.
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H. Fan, X. Niu, Q. Liu and W. Luk, "F-C3D: FPGA-based 3-dimensional convolutional neural network," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1-4, doi: 10.23919/FPL.2017.8056779.
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Liu, Q. and Qian, H. (2017), Fast and accurate circuit delay model for FPGA architectural exploration. IET Comput. Digit. Tech., 11: 117-123. https://doi.org/10.1049/iet-cdt.2016.0053
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T. Li and Q. Liu, "A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 5, pp. 1109-1113, May 2018, doi: 10.1109/TCAD.2017.2729348.
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Q. Liu, J. Liu, R. Sang, J. Li, T. Zhang and Q. Zhang, "Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1575-1579, Aug. 2018, doi: 10.1109/TVLSI.2018.2820016.
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B. Ning and Q. Liu, "Modeling and Efficiency Analysis of Clock Glitch Fault Injection Attack," 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, 2018, pp. 13-18, doi: 10.1109/AsianHOST.2018.8607175.
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J. Liu and Q. Liu, "Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix Updating," 2018 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, 2018, pp. 301-306, doi: 10.1109/FPL.2018.00058.
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J. Liu and Q. Liu, "Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network Training," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 362-365, doi: 10.1109/FPT.2018.00074.
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Li, H., Liu, Q. and Chen, F. (2018), Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. IET Comput. Digit. Tech., 12: 258-267. https://doi.org/10.1049/iet-cdt.2018.5101
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Q. Liu, P. Zhao and F. Chen, "A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits," in IEEE Access, vol. 7, pp. 44632-44644, 2019, doi: 10.1109/ACCESS.2019.2908088.
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Q. Liu, B. Ning and P. Deng, "Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks," in IEEE Access, vol. 7, pp. 141920-141928, 2019, doi: 10.1109/ACCESS.2019.2944024.
