F. Chen and Q. Liu, "Single-triggered hardware Trojan identification based on gate-level circuit structural characteristics," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050673.

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上一条:Q. Liu and H. Qian, "FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters," 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 29-29, doi: 10.1109/FCCM.2017.16. 下一条:H. Fan, X. Niu, Q. Liu and W. Luk, "F-C3D: FPGA-based 3-dimensional convolutional neural network," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1-4, doi: 10.23919/FPL.2017.8056779.